The present invention relates to computer graphics, and more particularly to occlusion culling during rendering in a computer graphics processing pipeline.
During graphics processing, a computer is commonly used to display three-dimensional representations of an object on a two-dimensional display screen. In a typical graphics computer, an object to be rendered is divided into a plurality of graphics primitives. The graphics primitives are basic components of a graphics picture and may be defined by geometry such as a point, line, vector, or polygon, such as a triangle. The graphics primitives are fed through a graphics pipeline where various types of processing occur and then commonly are displayed on an output device.
An example of a typical graphics pipeline 10 is shown in Prior Art FIG. 1 and comprises a transform/lighting unit 12 for converting input primitive data from one coordinate space to another coordinate space, and applying lighting to the transformed graphics primitives. During operation, the transform portion of unit 12 may be used to perform scaling, rotation, and projection of a set of three dimensional vertices from their local or model coordinates to the two dimensional window that will be used to display the rendered object. The lighting portion of unit 12 sets the color and appearance of a vertex based on various lighting schemes, light locations, ambient light levels, materials, and so forth. Thereafter, a rasterizer 14 is utilized to identify the picture elements (pixels) corresponding to each drawn primitive.
Still yet, shading operations 16 are performed to interpolate colors at each of the primitive""s pixels and a texture module 18 may perform conventional texture mapping. These may be combined to compute a color for each drawn pixel. The computation required may be complex, requiring expensive arithmetic and consuming considerable bandwidth from texture memory.
Towards the end of the graphics pipeline 10 after shading and texturing, a Z-value of each pixel of a primitive is tested in module 20. Such test includes a comparison of the Z-value of each pixel with a stored Z value which represents the nearest of the preceding primitives that overlapped the pixel. If the compared Z-value is in xe2x80x9cfrontxe2x80x9d, the color and Z-value are valid and are written. If not, the color and Z-value are not written, and instead discarded. As the speed of processors increase, the tests involving the Z-value of a pixel are performed more and more frequently, and the fraction of color and Z-values that are discarded also increases.
The fact that such prior art processing scheme is computing texture and color values, and then discarding them in such large quantities represents a waste. Various solutions have been set forth in the following publications:
N. Greene, M. Kass, and G. Miller. Hierarchical Z-buffer Visibility. SIGGRAPH proceedings 1993 (pages 231-238).
N. Greene, Hierarchical Polygon Tiling with Coverage Masks. SIGGRAPH proceedings 1996 (pages 65-74).
F. Xie and M. Shantz, Adaptive Hierarchical Visibility in a Tiled Architecture, Proceedings of Eurographics/SIGGRAPH workshop on Graphics Hardware, 1999, pages 75-84.
N. Greene, Occlusion Culling with Optimized Hierarchical Buffer, Visual Proceedings of ACM SIGGRAPH 1999 (page 261).
D. Bartz, M. Meissner, and T. Huttner, Extended Graphics Hardware for Occlusion Queries in OpenGL, Proceedings of Eurographics/SIGGRAPH workshop on Graphics Hardware, 1998, pages 97-104.
While the techniques set forth in the above publications accomplish their intended purposes, they are overly complicated and still render additional occluded pixels unnecessarily. There is thus a need for a way of minimizing unnecessary processing, i.e., reading of various values, and accelerate the rendering of occluded pixels.
A system, method and article of manufacture are afforded for providing an interlock module in a graphics pipeline. Initially, first information is received indicative of a first set of pixels that overlap a primitive. Such first set of pixels are currently being processed in the graphics pipeline. Also received is second information indicative of a second set of pixels that overlap the primitive. The second set of pixels are ready for being inputted in the graphics pipeline for processing. Thereafter, the first information and the second information are evaluated, and the second set of pixels is conditionally processed based on the evaluation.
In one embodiment, the processing may include Z-value culling and/or stencil culling. Further, the first and second information may take the form of masks.
As an option, an indication may be received as to the number of pixels in the first set of pixels that are currently being processed in the graphics pipeline. Further, each of the second set of pixels may be processed if the number of pixels equals zero (0). Such number of pixels may also be tracked using a variable. Optionally, the evaluation may include an OR function.